1. Field of the Invention
The present invention relates to techniques for creating low-power integrated circuits. In particular, the present invention relates to techniques designed for creating low-power integrated circuits using a power-gating technique.
2. Discussion of the Related Art
Power-gating is a circuit level technique applicable to, for example, multi-threshold CMOS (MTCMOS) circuits to reduce leakage power (i.e., to reduce power dissipation due to leakage current). In power-gating, a switch cell is introduced between a functional circuit and a power supply voltage reference or a ground voltage reference, so that the functional circuit can be selectively electrically connected or disconnected from a power source or the ground reference by deasserting or asserting a sleep signal. A switch cell may be implemented by a PMOS or a NMOS transistor, depending on whether the connection to the power supply voltage reference (VDD) or the ground voltage reference (VSS) is controlled by the switch cell.
Until recently, power gating is a coarse-grained technique—i.e., relatively few power domains are provided in a circuit block or module of an integrated circuit, and typically places the entire circuit block or module into a standby state. More recently, fine-grained power gating techniques (i.e., many more power domains are provided in a circuit block, and placing only a portion of the circuit block in a standby state) have been developed, so that each power domain controls the active or power saving modes of a small portion of the circuit block or module. As a result, during operation, many power domains of the circuit block may be independently put into a standby mode, while other power domains in the same circuit block are active. These techniques reduce leakage power while the circuit block or module is in an active state (i.e., “active leakage power reduction”).
Micro-architecture level techniques have been developed for power gating the execution units in microprocessors. Examples of such approaches include: (i) “Micro-architectural Techniques for Power Gating of Execution Units”, by Hu et al., ISLPED 2004 Proceedings, pp 32-37, and “Managing Static Leakage Energy in Microprocessor Functional Units”, by Dropsho et al., MICRO 2002 Proceedings, pp 321-332. Using dual-threshold domino logic circuits, these techniques provide analytical models for determining suitable sleep-mode activation policies for integer functional units of a microprocessor. However, both these techniques require adding significant amount of additional logic circuits to generate the sleep signal needed for power gating.
As another example, in “A Scheme to Reduce Active Leakage Power by Detecting State Transitions,” Usami et al. use a clock enable signal to power-gate the fan-in logic cones of clock-gated registers. This technique, however, leads to a significant increase in critical path delays and is recommended for use only in conjunction with burn-in testing.